MOS Current Mode Logic (MCML) is a differential logic family. MCML is beneficial for high speed mixed signal integrated circuits (ICs). It has been shown to provide a number of advantages over static CMOS including less power consumption at higher frequencies, less sensitivity to switching noise, and increased process voltage temperature (PVT) immunity.
Subthreshold Source Coupled Logic (STSCL) is also a differential logic family with similar circuit topology as MCML. However, STSCL is most beneficial for ultra-low power and low frequency applications. Depending on the leakage current, activity factor, and operation frequency, STSCL can have advantages (e.g. power reduction, tunability) over static CMOS.
Prior art current mode CMOS logic circuits are described for example in patent publication “CURRENT MODE LOGIC DIGITAL CIRCUITS”, US2009219054 (A1), Toumazou Christofer [GB], and Cannillo Francesco [GB]. It describes biasing and general design of MOS current more logic (MCML) including STSCL.